The present invention relates to digital to analog converters (DAC""s) and more particularly to resistor string type DAC""s with differential outputs adopted for IC fabrication.
Digital to analog converters are widely used in mixed-mode systems requiring monotonicity where the converter acts as an interface between the digital signal processing and analog signal processing components of such systems.
Differential DAC""s are often seen in high-speed mixed-mode systems to reduce the common-mode voltage noise thereby enhancing the performance of the system.
A typical differential R-DAC is the one shown in FIG. 1, using a tree structure switch matrix providing inherent decoding, and thus eliminating the need for a digital decoder. It uses a resistor voltage divider network connected between two reference voltages (VREFP and VREFN) to generate a complete set of voltages.
Each resistor tap corresponds to a resistor value of R. It requires 2 jumps of switches (the upper one moving down by one R and the lower one moving up by one R) to achieve 1 LSB(least significant bit) jump for every code transition.
One drawback of this circuit includes high component count: 2N resistors, 2xc3x97 (2N+1xe2x88x922) switches which increase area utilization. N is the resolution of the D-to-A converter.
A second drawback is that the voltages selected must propagate through N levels of switches before reaching outputs AOUTP and AOUTN. The delay through the decoding network is a limiting factor on the conversion speed of the DAC.
Another often seen differential R-DAC is shown in FIG. 2 using a digital decoder 10. This configuration also uses a resistor voltage divider network 12 between two reference voltages to generate a complete set of voltages. The voltage drop across each resistor is equal to 0.5 least significant bit (LSB) of output voltage change. In this configuration all the switches are connected to the outputs. The output is sampled by a N-to-2N digital decoder 10, illustrated as switches Q(1), Q(2), . . . Q(2Nxe2x88x921),Q(2N). Each switch taps a different point in the resistor string, so by closing a specific switch while other ones are open generates a unique analog voltage on node AOUTP and AOUTN. It requires 2 jumps of switches at a time to obtain 1 LSB jump.
The total number of switches required for this resistor string DAC with differential outputs is 2xc3x97(2N)= greater than (2N+1).
The main drawback of this circuit is that the 2N+1 switches resulting in a large capacitive load at the outputs, as well as large area utilization due to 2N resistors and switches.
Other DAC""s have been presented in the literature by:
[1] U.S. Pat. No. 6,297,759 by Lanny L. Lewyn, in which a DAC includes separate converter segments for converting the MSB""s and the next NSB""s of a digital word. The DAC provides a high conversion rate with very low glitch disturbance.
[2] U.S. Pat. No. 6,130,634 by Mark V. Wadshorth et,al, in which a R-DAC is presented with improved speed by tailoring the selection switch size to the node location.
[3] U.S. Pat. No. 5,495,245 by James J. Ashe, in which the number of resistors and switches required for a voltage scaling DAC is reduced by segmenting the voltage decrementing resistor string into two separate outer strings and an inner string.
[4] U.S. Pat. No. 5,252,975 by Tachio Yuassa et,al,in which DAC having 2 resistor networks:a high-order-bit side and a low-order-bit side which operate in response to high-order bits of a digital input signal and low-order bits thereof.
[5] Analog Integrated Circuit Design by David A. Johns and Ken Martin, showing Nyquist-Rate D/A Converters categorized in 4 main categories: decoder-based,binary-weighted, thermometer-code, and hybrid pp 433-466.
However none achieve low area utilization, due to large reduction of switches and faster conversion speed due to lesser parasitic capacitance in the signal path.
It is an object of one embodiment of the present invention to show a resistor string DAC architecture with differential outputs sharing the same set of switches through 2 levels of decoding.
It is another object of the present invention to show a reduction in the number of switches through a unique placement of tap points in the resistor string and the decoding logic.
These objects are achieved by using two switching networks one with a plurality of 2Nxe2x88x921+2 switches coupled to a first resistor string that provides a selectable tap from the resistor string to two inner nodes, and a second comprised of 4 switches coupled to the two inner nodes for connecting to the output terminals of the D/A converter.